As is generally known in the art, semiconductor memory devices are mainly classified into a volatile random access memory (RAM), which loses information stored therein when power is cut off, and non-volatile read only memory (ROM), which continuously retains information stored therein even if power is cut off. Volatile semiconductor RAM includes dynamic RAM (DRAM) and static RAM (SRAM). The non-volatile semiconductor ROM includes flash memory such as an electrically erasable and programmable ROM.
However, as generally known to those skilled in the art, even though the DRAM is a memory device having superior performance, the DRAM stores data using a capacitance effect and therefore it requires relatively high storage capacitance. Since the storage capacity of an electrical capacitor is directly proportional to the spacing between electrodes the material between electrodes and the surface area of the electrodes, DRAMs need relatively large areas just to accommodate the capacitors needed to store charges that represent data. Put another way, as a semiconductor data storage device, the DRAM presents a problem in view of high integration.
Prior art flash memory devices present a different set of problems. Flash memory requires operating voltage higher than supply voltage because the flash memory has a stacked structure of two gates. For this reason, the flash memory device must be equipped with a separate voltage-booster circuit in order to obtain voltages required for writing or erasing operations. In this regard, the flash memory device disturbs high integration of a circuit.
Relatively recent research has developed new highly integrated memory devices having a simple structure that provides a non-volatile memory. One example of a new highly integrated non-volatile memory device is a a phase change RAM device.
A phase change RAM device determines information stored in a cell according to a resistance difference between a crystalline state and an amorphous state of a phase change layer. This phase-change layer is interposed between electrodes and undergoes a phase change from the crystalline state to the amorphous state as current flows between the electrodes.
Phase-change memory devices employ a chalcogenide film as the phase-change layer. The chalcogenide film is a compound material layer consisting of germanium (Ge), stibium (Sb), and tellurium (Te). Electrical current through the material causes it to undergo a phase change between the crystalline state and the amorphous state by reason of Joule heat caused by the electrical current. The phase-change layer has a higher electrical resistance in the amorphous state than in the crystalline state. Information stored in the phase-change memory cell can be either a logic “1” or “0” by detecting the current flowing through the phase-change layer in writing or reading modes.
FIG. 1 is a sectional view of a conventional phase-change memory device.
As shown in FIG. 1, gates 4 are formed on a semiconductor substrate 1, and a junction area (not shown) is formed on the surface of the semiconductor substrate at both sides of the gate 4. An insulating interlayer 5 is formed on the entire surface of the semiconductor substrate 1 in such a manner that the insulating interlayer 5 covers the gates 4. A first tungsten plug 6a and a second tungsten plug 6b are formed at predetermined portions of the insulating interlayer 5 where a phase change cell is formed and a ground voltage (Vss) is applied, respectively.
A first oxide layer 7 is formed on the insulating interlayer 5 including the first and second tungsten plugs 6A and 6B. Although it is not shown in detail, in the first oxide layer 7, a dot-type metal pad 8 is formed in a predetermined area where the phase-change cell is formed, such that the dot-type metal pad 8 is in contact with the first tungsten plug 6A, and a bar-type ground line (Vss line) 9 is formed in a predetermined area to which a ground voltage is applied, such that the bar-type ground line is in contact with the second tungsten plug 6B.
A second oxide layer 10 is formed on the first oxide layer 7 including the metal pad 8 and the ground line 9. A plug-type bottom electrode 11 is formed in a predetermined area of the second oxide layer 10, onto which the phase-change cell will be formed, such that plug-type bottom electrode 11 is in contact with the metal pad 8.
A phase-change layer 12 and a top electrode 13 are sequentially stacked in a predetermined pattern on the second oxide layer 10, so as to be in contact with the bottom electrode 11, thereby forming the phase-change cell including the plug-type bottom electrode 11, phase-change layer 12 and top electrode 13 which have been sequentially stacked.
Then, a third oxide layer 14 is formed on the second oxide layer 10 so as to cover the phase-change cell, and a metal line 15 is formed on the third oxide layer 14 so as to be in contact with the top electrode 13.
Meanwhile, the conventional phase-change memory device requires a very high current (e.g. 1 mA or more) in order to achieve stable phase change. Therefore, in order to decrease the current required for the phase change of the phase-change layer, it is necessary to reduce the contact area between the phase-change layer and the electrodes.
The conventional exposure and etching techniques present limitations to reduce the contact area between the phase-change layer and the electrodes.
In addition, according to the conventional phase-change memory device shown in FIG. 1, although the phase-change layer 12 is in contact with the top electrode 13 as well as the bottom electrode 11, only the area being in contact with the bottom electrode 11 is generally used as a phase-change area because it is impossible to use both of the contact areas as phase-change areas. Accordingly, the phase change of the phase-change layer 12 depends on a contact resistance between the phase-change layer 12 and the bottom electrode 11. However, as described above, because of the limitations of the conventional techniques, it is difficult to stably form the contact area between the phase-change layer 12 and the bottom electrode 11, so that variation of the contact resistance becomes increased, thereby deteriorating reliability of products.